1. Field of the Invention
The invention relates to a communication interface device and a communication method, and particularly to a communication interface device and a communication method capable of communication via plural different interface protocols.
2. Related Art
Conventionally, there has been widely used various serial bus interfaces such as Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I2C) in communication between CPU and peripheral devices or communication among chips. The SPI is known as one of three-wire serial bus interfaces and the I2C is known as one of two-wire serial bus interfaces, and both are widely used. Thus, in recent years, the interface circuits for both the two-wire system and the three-wire system are mounted on many integrated circuits so as to adapt to the both.
As a method for recognizing two types of interface protocols, conventionally a terminal for recognizing (selecting) a protocol is provided in addition to a terminal required for serial bus communication, and a selection signal for selecting a protocol is input into the additional terminal from the outside to select and operate either the two-wire circuit or the three-wire circuit.
Alternately, there is proposed a method for automatically recognizing two types of interface protocols. For example, Japanese Patent Application Laid-Open (JP-A) No. 2002-232508 discloses a method for determining a protocol from a chip enable signal by sharing a clock terminal and a data terminal between the two-wire system and the three-wire system. Further, JP-A No. 63-250759 discloses a method for recognizing a protocol by transmitting a special signal for recognizing a protocol (dummy access) before data transfer.
However, the method disclosed in JP-A No. 2002-232508 has a problem leading to an erroneous operation.
This erroneous operation will be described with reference to FIGS. 7 and 8A-B.
FIG. 7 shows an example of a configuration of a communication circuit that performs communication between a CPU 300 and Large Scale Integration Circuits (LSIs) 301, 302 by using the method disclosed in JP-A No. 2002-232508. The LSIs 301 and 302 are respectively configured operable in both the I2C and SPI interface protocols.
A clock line 305 for transmitting a clock signal clk and a data line 306 for transmitting a data signal Data respectively branch into two and are connected to the LSI 301 and the LSI 302. Thus, a configuration is made such that a clock signal clk to be supplied to the LSI 301 and a clock signal clk to be supplied to the LSI 302 are input from a common terminal and a data signal Data to be transferred to the LSI 301 and a data signal Data to be transferred to the LSI 302 are input from a common terminal (which is different from the terminal into which the clock signals clk are input) among the terminals into which signals are input from the CPU 300.
A chip select line 303 transmits a chip selection signal cs1 to the LSI 302. A chip select line 304 transmits a chip selection signal cs2 to the LSI 301.
When the chip selection signal cs1 is at the Low level, SPI communication is performed between the LSI 302 and the CPU 300. The chip selection signal cs2 is set at the High level during the period in which the SPI communication is performed between the LSI 302 and the CPU 300 such that the LSI 301 does not operate (does not perform communication).
When the chip selection signal cs2 is at the Low level, the SPI communication is performed between the LSI 301 and the CPU 300. The chip selection signal cs1 is set at the High level during the period in which the SPI communication is made between the LSI 301 and the CPU 300 such that the LSI 302 does not operate (does not perform communication).
The communication circuit is connected with a register and the like, and data indicated by the data signal output from the LSI which is selected and operated by the chip selection signal cs1 or cs2 among the LSI 301 and the LSI 302 is written into the connected register.
An explanation will be made of a case in which data 0xff is written in an address 0x11 of the register via the LSI 302 through the SPI communication.
FIG. 8A is a time chart of the signals to the LSI 302, and FIG. 8B is a time chart of the signals to the LSI 301. As shown in FIG. 8A, the chip selection signal cs1 is first set at the Low level for operating the LSI 302 in order to transfer the address 0x11, and after the address transfer, data transfer is performed.
In this way, although normal communication appears to be possible in terms of only the LSI 302, since the terminal for inputting the data signal and the terminal for inputting the clock signal are shared between the LSIs, the same signals other than the chip selection signal cs2 are also input into the LSI 301.
Since the chip selection signal cs2 is fixed at the High level, the SPI communication will not be established for the LSI 301. However, from the viewpoint of operation in the I2C interface protocol, when the data signal Data changes to Low while the clock signal clk is at High, the I2C start condition is satisfied.
Further, an LSI-specific slave address is assigned to each of the LSIs in the I2C protocol. Typically, a slave address indicating a communication destination is transmitted after the start condition in the I2C protocol. However, in this example, in a case in which the slave address specific to the LSI 301 is 0x1f, when a signal matching with the slave address 0x1f has been transmitted as the data signal Data after the start condition as shown in FIG. 8B, the LSI 301 may erroneously recognize that an I2C access has been made.
As a result, the LSI 301 tries to transmit a Low-level signal as acknowledgement to the CPU 300 via the data line 306 in a period circled in FIG. 8B. At this time, the CPU 300 tries to transmit data to the LSI 302 in the SPI protocol; however, since the LSI 301 tries to set the data line 306 at the Low level, the data for the LSI 302 may be corrupted in the acknowledgement period. In other words, since the CPU operates in a High drive and the LSI 301 operates in a Low drive in the acknowledgement period, the communication quality remarkably deteriorates, which leads to an erroneous operation.
This problem occurs because the terminal for inputting the data signal to be supplied to the LSI 301 and the terminal for inputting the data signal to be supplied to the LSI 302 are common, and further the terminal for inputting the clock signal to be supplied to the LSI 301 and the terminal for inputting the clock signal to be supplied to the LSI 302 are common.
The method described in JP-A No. 63-250759 has a problem that since a protocol is recognized via a special access (dummy access), when plural Leis are connected to an interface bus (for example, when a LSI requiring dummy access and a LSI not requiring dummy access coexist in the plural Leis), control therefore is complicated.